UVH_GR1_TLB_INT0_CONFIG_P_MASK  335 arch/ia64/include/asm/uv/uv_mmrs.h #define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
UVH_GR1_TLB_INT0_CONFIG_P_MASK 1278 arch/x86/include/asm/uv/uv_mmrs.h #define UVH_GR1_TLB_INT0_CONFIG_P_MASK			0x0000000000002000UL