UVH_GR0_TLB_INT1_CONFIG_P_MASK  297 arch/ia64/include/asm/uv/uv_mmrs.h #define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
UVH_GR0_TLB_INT1_CONFIG_P_MASK  806 arch/x86/include/asm/uv/uv_mmrs.h #define UVH_GR0_TLB_INT1_CONFIG_P_MASK			0x0000000000002000UL