UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT  759 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x00000000
UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT  534 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT  566 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT  568 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT  661 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT                                                              0x0
UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 1181 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT                                                              0x0
UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 2687 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT                                                              0x0
UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 2691 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT                                                              0x0