UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT  751 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x00000000
UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT  528 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT  560 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT  562 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT  652 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT                                                          0x0
UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 1172 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT                                                          0x0
UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 2678 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT                                                          0x0
UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 2682 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT                                                          0x0