UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT  749 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x00000000
UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT  524 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT  556 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT  558 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT  646 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT                                                          0x0
UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 1166 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT                                                          0x0
UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 2672 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT                                                          0x0
UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 2676 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT                                                          0x0