UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK  734 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK  101 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK  101 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK  101 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK  200 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK                                                               0x00E00000L
UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK  422 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK                                                               0x00E00000L