UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK  753 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1
UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK  751 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1
UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK  508 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK                                                                    0x00000001L
UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 3265 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK                                                                    0x00000001L
UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 2139 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK                                                                    0x00000001L