UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 767 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 765 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 515 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 3272 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 2146 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L