UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT  766 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT  764 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT  486 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT                                                             0x6
UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 3242 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT                                                             0x6
UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 2116 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT                                                             0x6