UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK  755 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2
UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK  753 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2
UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK  509 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK                                                                    0x00000002L
UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 3266 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK                                                                    0x00000002L
UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 2140 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK                                                                    0x00000002L