UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 759 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8 UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 757 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8 UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 511 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 3268 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 2142 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L