UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK  533 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK                                                            0x02000000L
UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 3290 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK                                                            0x02000000L
UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 2164 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK                                                            0x02000000L