UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK  527 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK                                                           0x00080000L
UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 3284 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK                                                           0x00080000L
UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 2158 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK                                                           0x00080000L