UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT  498 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT                                                         0x12
UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 3254 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT                                                         0x12
UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 2128 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT                                                         0x12