UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT  772 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT  770 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT  489 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT                                                             0x9
UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 3245 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT                                                             0x9
UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 2119 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT                                                             0x9