UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK  771 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK  769 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK  517 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK                                                               0x00000200L
UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 3274 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK                                                               0x00000200L
UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 2148 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK                                                               0x00000200L