UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK  757 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4
UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK  755 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4
UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK  510 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK                                                                    0x00000004L
UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 3267 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK                                                                    0x00000004L
UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 2141 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK                                                                    0x00000004L