UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT  501 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT                                                            0x15
UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 3257 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT                                                            0x15
UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 2131 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT                                                            0x15