UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT  780 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT  778 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT  493 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT                                                             0xd
UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 3249 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT                                                             0xd
UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 2123 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT                                                             0xd