UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK  779 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000
UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK  777 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000
UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK  521 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK                                                               0x00002000L
UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 3278 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK                                                               0x00002000L
UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 2152 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK                                                               0x00002000L