UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT  764 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT  762 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT  485 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT                                                                  0x5
UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 3241 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT                                                                  0x5
UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 2115 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT                                                                  0x5