UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 763 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20 UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 761 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20 UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 513 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 3270 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 2144 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L