UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT  776 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT  774 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT  491 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT                                                             0xb
UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 3247 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT                                                             0xb
UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 2121 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT                                                             0xb