UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK  775 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800
UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK  773 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800
UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK  519 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK                                                               0x00000800L
UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 3276 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK                                                               0x00000800L
UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 2150 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK                                                               0x00000800L