UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK  761 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10
UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK  759 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10
UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK  512 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK                                                                    0x00000010L
UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 3269 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK                                                                    0x00000010L
UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 2143 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK                                                                    0x00000010L