UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK  781 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x4000
UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK  522 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK                                                                   0x00004000L
UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 3279 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK                                                                   0x00004000L
UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 2153 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK                                                                   0x00004000L