UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT  507 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT                                                             0x1b
UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 3263 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT                                                             0x1b
UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 2137 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT                                                             0x1b