UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK  524 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK                                                                    0x00010000L
UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 3281 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK                                                                    0x00010000L
UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 2155 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK                                                                    0x00010000L