UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK  244 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK                                                                  0x00040000L
UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK  472 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK                                                                  0x00040000L
UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 3227 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK                                                                  0x00040000L
UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 2101 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK                                                                  0x00040000L