UVD_SUVD_CGC_GATE__SCM_HEVC_MASK  743 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400
UVD_SUVD_CGC_GATE__SCM_HEVC_MASK  745 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400
UVD_SUVD_CGC_GATE__SCM_HEVC_MASK  236 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK                                                                      0x00000400L
UVD_SUVD_CGC_GATE__SCM_HEVC_MASK  464 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK                                                                      0x00000400L
UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 3219 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK                                                                      0x00000400L
UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 2093 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK                                                                      0x00000400L