UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK  797 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x40
UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK  261 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK                                                                   0x00000040L
UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK  553 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK                                                                   0x00000040L
UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 3312 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK                                                                   0x00000040L
UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 2186 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK                                                                   0x00000040L