UVD_SUVD_CGC_CTRL__SRE_MODE_MASK  785 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1
UVD_SUVD_CGC_CTRL__SRE_MODE_MASK  779 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1
UVD_SUVD_CGC_CTRL__SRE_MODE_MASK  255 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK                                                                      0x00000001L
UVD_SUVD_CGC_CTRL__SRE_MODE_MASK  547 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK                                                                      0x00000001L
UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 3306 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK                                                                      0x00000001L
UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 2180 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK                                                                      0x00000001L