UVD_STATUS__VCPU_REPORT__SHIFT 693 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_STATUS__VCPU_REPORT__SHIFT 0x00000001 UVD_STATUS__VCPU_REPORT__SHIFT 632 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 UVD_STATUS__VCPU_REPORT__SHIFT 694 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 UVD_STATUS__VCPU_REPORT__SHIFT 696 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 UVD_STATUS__VCPU_REPORT__SHIFT 752 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 UVD_STATUS__VCPU_REPORT__SHIFT 1279 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 UVD_STATUS__VCPU_REPORT__SHIFT 2903 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 UVD_STATUS__VCPU_REPORT__SHIFT 1735 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1