UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT  629 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x00000000
UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT  110 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT  122 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT  124 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT  340 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT                                                                    0x0
UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT  701 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT                                                                    0x0
UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 1737 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT                                                                    0x0
UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 2984 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT                                                                    0x0