UVD_SEMA_CMD__WR_PHASE__SHIFT  625 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x00000004
UVD_SEMA_CMD__WR_PHASE__SHIFT   34 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
UVD_SEMA_CMD__WR_PHASE__SHIFT   34 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
UVD_SEMA_CMD__WR_PHASE__SHIFT   34 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
UVD_SEMA_CMD__WR_PHASE__SHIFT  293 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SEMA_CMD__WR_PHASE__SHIFT                                                                         0x4
UVD_SEMA_CMD__WR_PHASE__SHIFT 3153 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SEMA_CMD__WR_PHASE__SHIFT                                                                         0x4
UVD_SEMA_CMD__WR_PHASE__SHIFT 2952 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SEMA_CMD__WR_PHASE__SHIFT                                                                         0x4