UVD_SEMA_CMD__VMID_EN__SHIFT  621 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x00000007
UVD_SEMA_CMD__VMID_EN__SHIFT   38 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
UVD_SEMA_CMD__VMID_EN__SHIFT   38 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
UVD_SEMA_CMD__VMID_EN__SHIFT   38 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
UVD_SEMA_CMD__VMID_EN__SHIFT  295 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SEMA_CMD__VMID_EN__SHIFT                                                                          0x7
UVD_SEMA_CMD__VMID_EN__SHIFT 3155 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SEMA_CMD__VMID_EN__SHIFT                                                                          0x7
UVD_SEMA_CMD__VMID_EN__SHIFT 2954 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SEMA_CMD__VMID_EN__SHIFT                                                                          0x7