UVD_SEMA_CMD__REQ_CMD__SHIFT  619 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x00000000
UVD_SEMA_CMD__REQ_CMD__SHIFT   32 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
UVD_SEMA_CMD__REQ_CMD__SHIFT   32 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
UVD_SEMA_CMD__REQ_CMD__SHIFT   32 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
UVD_SEMA_CMD__REQ_CMD__SHIFT  292 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_SEMA_CMD__REQ_CMD__SHIFT                                                                          0x0
UVD_SEMA_CMD__REQ_CMD__SHIFT 3152 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_SEMA_CMD__REQ_CMD__SHIFT                                                                          0x0
UVD_SEMA_CMD__REQ_CMD__SHIFT 2951 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_SEMA_CMD__REQ_CMD__SHIFT                                                                          0x0