UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 607 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000000 UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 628 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 690 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 692 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 748 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 1275 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 2893 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 2922 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0