UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK   62 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK                                                                0x0000000CL
UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 1498 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK                                                                0x0000000CL
UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 1501 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK                                                                0x0000000CL