UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 63 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 1499 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 1502 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L