UVD_MPC_SET_MUX__SET_2__SHIFT  533 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x00000006
UVD_MPC_SET_MUX__SET_2__SHIFT  518 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
UVD_MPC_SET_MUX__SET_2__SHIFT  550 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
UVD_MPC_SET_MUX__SET_2__SHIFT  552 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
UVD_MPC_SET_MUX__SET_2__SHIFT  636 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_2__SHIFT                                                                         0x6
UVD_MPC_SET_MUX__SET_2__SHIFT 1143 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_2__SHIFT                                                                         0x6
UVD_MPC_SET_MUX__SET_2__SHIFT 2649 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_2__SHIFT                                                                         0x6
UVD_MPC_SET_MUX__SET_2__SHIFT 2884 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUX__SET_2__SHIFT                                                                         0x6