UVD_MPC_SET_MUX__SET_1__SHIFT  531 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x00000003
UVD_MPC_SET_MUX__SET_1__SHIFT  516 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
UVD_MPC_SET_MUX__SET_1__SHIFT  548 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
UVD_MPC_SET_MUX__SET_1__SHIFT  550 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
UVD_MPC_SET_MUX__SET_1__SHIFT  635 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1__SHIFT                                                                         0x3
UVD_MPC_SET_MUX__SET_1__SHIFT 1142 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1__SHIFT                                                                         0x3
UVD_MPC_SET_MUX__SET_1__SHIFT 2648 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1__SHIFT                                                                         0x3
UVD_MPC_SET_MUX__SET_1__SHIFT 2883 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUX__SET_1__SHIFT                                                                         0x3