UVD_MPC_SET_MUX__SET_1_MASK 530 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L UVD_MPC_SET_MUX__SET_1_MASK 515 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 UVD_MPC_SET_MUX__SET_1_MASK 547 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 UVD_MPC_SET_MUX__SET_1_MASK 549 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 UVD_MPC_SET_MUX__SET_1_MASK 638 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L UVD_MPC_SET_MUX__SET_1_MASK 1145 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L UVD_MPC_SET_MUX__SET_1_MASK 2651 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L UVD_MPC_SET_MUX__SET_1_MASK 2886 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L