UVD_MPC_SET_MUXB1__VARB_6__SHIFT 525 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x00000006 UVD_MPC_SET_MUXB1__VARB_6__SHIFT 510 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 UVD_MPC_SET_MUXB1__VARB_6__SHIFT 542 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 UVD_MPC_SET_MUXB1__VARB_6__SHIFT 544 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 UVD_MPC_SET_MUXB1__VARB_6__SHIFT 628 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 UVD_MPC_SET_MUXB1__VARB_6__SHIFT 1135 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 UVD_MPC_SET_MUXB1__VARB_6__SHIFT 2641 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 UVD_MPC_SET_MUXB1__VARB_6__SHIFT 2876 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6