UVD_MPC_SET_MUXB1__VARB_5__SHIFT  523 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x00000000
UVD_MPC_SET_MUXB1__VARB_5__SHIFT  508 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
UVD_MPC_SET_MUXB1__VARB_5__SHIFT  540 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
UVD_MPC_SET_MUXB1__VARB_5__SHIFT  542 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
UVD_MPC_SET_MUXB1__VARB_5__SHIFT  627 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT                                                                      0x0
UVD_MPC_SET_MUXB1__VARB_5__SHIFT 1134 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT                                                                      0x0
UVD_MPC_SET_MUXB1__VARB_5__SHIFT 2640 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT                                                                      0x0
UVD_MPC_SET_MUXB1__VARB_5__SHIFT 2875 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT                                                                      0x0