UVD_MPC_SET_MUXB0__VARB_4__SHIFT 521 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x00000018 UVD_MPC_SET_MUXB0__VARB_4__SHIFT 506 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 UVD_MPC_SET_MUXB0__VARB_4__SHIFT 538 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 UVD_MPC_SET_MUXB0__VARB_4__SHIFT 540 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 UVD_MPC_SET_MUXB0__VARB_4__SHIFT 620 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 UVD_MPC_SET_MUXB0__VARB_4__SHIFT 1127 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 UVD_MPC_SET_MUXB0__VARB_4__SHIFT 2633 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 UVD_MPC_SET_MUXB0__VARB_4__SHIFT 2868 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18