UVD_MPC_SET_MUXB0__VARB_3__SHIFT  519 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x00000012
UVD_MPC_SET_MUXB0__VARB_3__SHIFT  504 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
UVD_MPC_SET_MUXB0__VARB_3__SHIFT  536 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
UVD_MPC_SET_MUXB0__VARB_3__SHIFT  538 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
UVD_MPC_SET_MUXB0__VARB_3__SHIFT  619 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT                                                                      0x12
UVD_MPC_SET_MUXB0__VARB_3__SHIFT 1126 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT                                                                      0x12
UVD_MPC_SET_MUXB0__VARB_3__SHIFT 2632 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT                                                                      0x12
UVD_MPC_SET_MUXB0__VARB_3__SHIFT 2867 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT                                                                      0x12