UVD_MPC_SET_MUXB0__VARB_2__SHIFT 517 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0x0000000c UVD_MPC_SET_MUXB0__VARB_2__SHIFT 502 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc UVD_MPC_SET_MUXB0__VARB_2__SHIFT 534 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc UVD_MPC_SET_MUXB0__VARB_2__SHIFT 536 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc UVD_MPC_SET_MUXB0__VARB_2__SHIFT 618 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc UVD_MPC_SET_MUXB0__VARB_2__SHIFT 1125 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc UVD_MPC_SET_MUXB0__VARB_2__SHIFT 2631 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc UVD_MPC_SET_MUXB0__VARB_2__SHIFT 2866 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc