UVD_MPC_SET_MUXB0__VARB_1__SHIFT  515 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x00000006
UVD_MPC_SET_MUXB0__VARB_1__SHIFT  500 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
UVD_MPC_SET_MUXB0__VARB_1__SHIFT  532 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
UVD_MPC_SET_MUXB0__VARB_1__SHIFT  534 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
UVD_MPC_SET_MUXB0__VARB_1__SHIFT  617 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT                                                                      0x6
UVD_MPC_SET_MUXB0__VARB_1__SHIFT 1124 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT                                                                      0x6
UVD_MPC_SET_MUXB0__VARB_1__SHIFT 2630 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT                                                                      0x6
UVD_MPC_SET_MUXB0__VARB_1__SHIFT 2865 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT                                                                      0x6