UVD_MPC_SET_MUXB0__VARB_0__SHIFT 513 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x00000000 UVD_MPC_SET_MUXB0__VARB_0__SHIFT 498 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 UVD_MPC_SET_MUXB0__VARB_0__SHIFT 530 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 UVD_MPC_SET_MUXB0__VARB_0__SHIFT 532 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 UVD_MPC_SET_MUXB0__VARB_0__SHIFT 616 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 UVD_MPC_SET_MUXB0__VARB_0__SHIFT 1123 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 UVD_MPC_SET_MUXB0__VARB_0__SHIFT 2629 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 UVD_MPC_SET_MUXB0__VARB_0__SHIFT 2864 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0